s5cs31 fetch decode execute cycle
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A central processing unit leads probably the most repetitive existence know to man (or woman). It does the same thing, nanosecond after nanosecond, never gets tired and never makes a mistake. Amazing. In this lesson, we investigate the cycle of its life.
We are learning ...
About the Fetch, Decode, Execute cycle
So that we can ...
State and describe the stages in the Fetch, Decode, eXecute (FDX) cycle
Explain Interrupt Service Routines (ISR)
Remember that the operation of a von Neumann machineI have no idea what this means requires that both instructions and data are accessible from the same data bus. Therefore, the Fetch (Decode) Execute cycle can only work with these so-called 'Stored Program Concept' machines.
Activity 1
The Fetch (Decode) Execute Cycle
In a previous topic, we learnt about the operation of the processor, how it utilised its connection to the components on the motherboard in order to carry out its tasks. However, we didn't consider the sequence in which it carries out those tasks. Firstly, look at the following animation. You will need to enlarge it so you can read it better.
The Fetch (Decode) Execute Cycle
Click to enlarge, 'cause it's a bit small.
You'll notice the strange notation used to represent the separate stages in the Fetch (Decode) Execute cycle. This is called register transfer notationI have no idea what this means and is commonly used to denote data flowing between registers and memory in the processor. In essence ...
Stages 1, 2 and 3 : Fetch : Retrieve the next instruction from memory
MAR ← [PC]
PC ← [PC] + 1
MBR ← [Memory]addressed
CIR ← [MBR]
Stage 4 : Decode : Look up the current instruction in the instruction set
Stage 5 : Execute : Carry out the instruction, retrieving more values from memory if necessary
Yes, but I'd still make some notes!
Yes and no. This is a grossly over-simplistic view of this processes - in reality, the processor is doing a lot more work than this keeping track of the operating system and the hardware for instance.
Task 1.1 An alternative view
STAGE 1
Make sure you have taken some notes from the animation you watched. Pay particular attention to the register transfer notation - you could well be asked about this in the examination (and the test 😉).
STAGE 2
Look carefully at the following diagram of the Fetch (Decode) Execute cycle which includes more complications like Interrupts.
FDX Cycle
Now download the Fetch (Decode) Execute Cycle worksheet. Use the diagram to help you to complete the blank version on the worksheet.
OUTCOME : Annotated FDX diagram
Virtually all computer systems provide a mechanism for handling interrupts from ...
System timers (to indicate that an event should be carried out)
Input / output devices (to indicate that normal operation has completed or an error has occurred)
Software applications (generally mathematical errors)
Hardware failure (generally a catastrophe)
Once the processor receives an interrupt from the 'device' (via a Programmable Interrupt Controller or PIC), the processor will respond by suspending its current activities, saving its current state and executing a function called an Interrupt Service Routine, or ISR, to deal with the event. After the interrupt is handled, control is passed back to the previous activity. High priority interrupts are dealt with before low priority ones, as you might expect.
Interrupts in computer systems can either be vectored or polled. In a vectored interrupt, the device directs the processor towards an appropriate Interrupt Service Routine whereas in polled interrupt, a single interrupt service routine needs to 'poll' the devices to determine which one initiated the interrupt.
Interrupts are a normal part of computation - they do not necessarily indicate errors
Vectored interrupts require that each device be assigned a unique identifier called an IRQ (Interrupt ReQuest). The processor knows the address of the Interrupt Service Routine in advance; all it needs is the IRQ code from the device and it can look up the ISR memory address in its 'Interrupt-Vector Table' and execute the interrupt by setting the program counter to the memory address of the ISR.
The original (i.e. old) PC based on 16-bit ISA (Industry Standard Architecture) had 16 hardware interrupt lines, maintained, originally, by two Programmable Interrupt Controllers (PIC) which are still available for legacy reasons even in today's PCs...
IRQ 00 : System timer
IRQ 01 : Keyboard on PS/2
IRQ 02 : Cascades signals from IRQ 8 to 15 (slave PIC), generally hidden
IRQ 03 : Serial Port
IRQ 04 : Serial Port
IRQ 05 : Parallel port / sound card
IRQ 06 : Floppy disk
IRQ 07 : Parallel port
IRQ 08 : Real-time clock
IRQ 09 : (Open)
IRQ 10 : (Open)
IRQ 11 : (Open)
IRQ 12 : Mouse on PS/2
IRQ 13 : CPU Numeric Processor
IRQ 14 : Primary ATA HDD
IRQ 15 : Secondary ATA HDD
... although very few of these legacy IRQs are used these days ...
Screenshot of msdiag32.exe from my laptop
More modern PCI architectures (using APIC, Advanced Programmable Interrupt Controller) increased the theoretical number of hardware IRQ to 24 helping to avoid IRQ sharing / conflicts and enable connectivity of more hardware devices. IRQs above 23 are maintained dynamically by the operating system.
Task 1.2 Excuse me for interrupting ...
Answer the following questions in your notebooks.
1
Give examples of the four classes of interrupts including their priority.
2
Describe, in your own words, how an interrupt is handled.
3
Describe the difference between a vectored interrupt and a polled interrupt.
4
What is an Interrupt Service Routine?
5
How many hardware interrupts did the original x86 PC handle?
OUTCOME : Answers to questions about Interrupts.
Extension Activities
How about this?
Read more about the Fetch Decode Execute cycle at Computer Science from the Bottom Up which also has a neat section on Pipelining (and is available as a free PDF book - well worth downloading!)
What's next?
Before you hand your book in for checking, make sure you have completed all the work required and that your book is tidy and organised. Your book will be checked to make sure it is complete and you will be given a spicy grade for effort.
Before you hand your book in for checking, make sure you have completed all the work required and that your book is tidy and organised. Your book will be checked to make sure it is complete and you will be given a spicy grade for effort.
END OF TOPIC ASSESSMENT
Last modified: February 14th, 2024
